SWI3 uses a wrong interrupt vector

[Rhialto]

Hi! Thanks for providing your core. I am creating a SuperPET aka MicroMainFrame 9000, which is a Commodore PET with an additional board with memory and a 6809e cpu. Another addition makes that it can run OS-9 (called Super-OS/9).

Unfortunately, Super-OS/9 did not boot. Eventually it went off into executing nonsense code. I traced this to the SWI3 instruction (which might be used in Super-OS/9 only, and perhaps not in base OS-9). It used an incorrect vector, viz. the one for SWI.

The problem is in this code:

3825     CPUSTATE_SWI_START:
3826     begin
3827         addr_nxt = pc;
3828         tmp_nxt = 16'H00FF; // Save to the S stack, PC, U, Y, X, DP, B, A,      CC
3829    
3830         NextState_nxt = CPUSTATE_IRQ_DONTCARE2;
3831         rAVMA = 1'b1;
3832         CpuState_nxt = CPUSTATE_IRQ_DONTCARE;
3833         if (InstPage3)
3834             IntType_nxt = INTTYPE_SWI3;
3835         if (InstPage2)
3836             IntType_nxt = INTTYPE_SWI2;
3837         else
3838             IntType_nxt = INTTYPE_SWI;
3839             
3840         cc_nxt[CC_E_BIT] = 1'b1;
3841     end

There should be an else on line 3835. (As far as I can tell, InstPage2 and InstPage3 cannot be true at the same time)
With the code as shown, SWI3 has InstPage3 = 1 and InstPage2 = 0, so the final else IntType_nxt = INTTYPE_SWI; takes effect, causing the use of the wrong interrupt vector.

I will submit a merge request in a moment (#6). I verified that Super-OS/9 boots with this change.

[Rhialto]

Additionally (it is not worth opening a separate issue for this I think), this comment seems incorrect:

  82 // Bus control
  83 // BS    BA
  84 //  0     0   normal (CPU running, CPU is master)
  85 //  0     1   Interrupt Ack
  86 //  1     0   Sync Ack
  87 //  1     1   CPU has gone high-Z on A, D, R/W

The middle two cases are swapped, according to the references I have. Fortunately the actual code matches the references, and not this comment.