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It seems a bit odd to support atomic instructions on a single-threaded target without peripherals, so I'm wondering what was the rationale behind having it anyway? I couldn't find any explanation for it anywhere. The only plausible explanation I have is that it helps to get more compact code for fetch/increment/store sequences, but that needs explicit atomic usage since LLVM right now does not promote such sequences to relaxed atomics automatically and I'm not sure they would be open to. |
Answered by
koute
Apr 16, 2026
Replies: 1 comment
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Compatibility. Same reason as to why single-threaded WASM target supports them. There's no reason not to support them. Code in the wild often uses atomics, and we want to be able to compile it. |
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Answer selected by
nazar-pc
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Compatibility. Same reason as to why single-threaded WASM target supports them.
There's no reason not to support them. Code in the wild often uses atomics, and we want to be able to compile it.