R&D Video Specialist @ Cires21 · The Community Of Madrid, Spain
I build and maintain scalable and composable broadcast-grade video pipelines and the HPC infrastructure underneath them.
- Codec & pipeline engineering — Deep expertise spanning across multiple video broadcast pipelines and workflows.
- Hardware-accelerated transcoding — NVIDIA NVENC/CUDA, Intel QSV, NETINT Quadra VPUs, among others.
- Broadcast transport — SMPTE ST 2110, ST 2110-22 JPEG XS, NMOS (IS-04/IS-05), DeckLink/BMD SDI capture, etc.
- HPC & cluster systems — Slurm, InfiniBand/RDMA, GPU cluster architecture (DGX/HGX), Linux kernel internals, etc.
- Leading encoder roadmap work across multiple hardware-accelerated trans-code and delivery backends and pipelines at Cires21
- Kernel-bypass transport (AF_XDP/eBPF, DPDK) for ST 2110 media delivery and beyond
- Benchmarking ASIC VPUs vs. GPU/CPU encoding (VMAF, power efficiency) — featured in a Cires21/NETINT white paper and on the Voices of Video podcast
- Gists on GPU/encoder tooling: Intel QSV-enabled FFmpeg builds,
nvidia-docker2setup, Skylake+ iGPU tuning (GuC/HuC firmware), Southern Islands AMD DPM fixes — see gists