cpu_soc connects the pipelined core's instruction and data channels to one
registered-response fabric through cpu_bus_arbiter. Data wins simultaneous
requests; an accepted owner retains the fabric until its response is consumed.
Program ROM, byte-write SRAM, UART, timer, GPIO, and unmapped-error targets use the
map in memory-map.md.
The UART implements 8-N-1 TX with a 16-bit cycles-per-bit-minus-one divider. A
TXDATA request waits while busy. byte_valid_o pulses at register acceptance for
cycle-independent simulation capture; the same byte is shifted physically on TX.
The timer has a 64-bit enabled counter and atomically committed compare value. Pending is sticky and RW1C. Clearing while the comparison remains true suppresses reassertion until a future compare is committed or count becomes less than compare.
GPIO is parameterized from 1 to 32 bits, synchronizes inputs through two flops, and provides output, direction, atomic set, and atomic clear registers. Upper absent bits read zero.
Integration regressions preload the actual fabric ROM and execute:
- demo: 112 retirements match the emulator and UART bytes match;
- timer_soc: timer wakes HALT, handler clears pending, and 133 instructions retire;
- gpio_soc: output
0x5a, direction0xff, and 203 instructions retire.