CPU

cpu is a custom 32-bit processor with an assembler, emulator, SystemVerilog implementation, FPGA build, and open ASIC synthesis flow.

The project implements the CPU-32 ISA, a three-stage in-order core, a Rust assembler/flat-binary builder and reference emulator, UART/timer/GPIO peripherals, random differential testing, bounded formal proofs, a placed-and-routed TinyFPGA BX target, and Sky130 standard-cell mappings. It has not been tested on a physical FPGA, and the ASIC flow has not completed physical signoff.

Demonstration

The demo image runs in the emulator, RTL SoC, and ASIC gate simulation, and is also packaged into the FPGA bitstream. Its UART output is:

Hello from cpu.

make demo-emu   # assemble and run the Rust reference model
make sim        # integrated RTL, byte-exact UART and emulator trace comparison
make trace      # also retain build/soc-trace.log
make wave       # retain build/cpu.vcd

Architecture

• 32-bit little-endian, byte-addressed architecture
• 16 integer registers with hardwired-zero r0
• fixed 32-bit instructions; 50 base mnemonics
• three stages: fetch, decode/execute, memory/writeback
• forwarding, load-use stalls, redirect epochs, and precise retirement
• byte, halfword, and word loads/stores with alignment traps
• precise exceptions, MRET, timer/external interrupts, and HALT wakeup
• separate valid/ready instruction and data ports with variable-latency responses
• shared SoC fabric with ROM, SRAM, UART TX, 64-bit timer, and GPIO
• no caches, MMU, speculation, floating point, or hidden platform dependencies

flowchart LR
  ASM["CPU-32 assembly"] --> AS["Rust assembler / binary builder"]
  AS --> BIN["Flat little-endian image"]
  BIN --> EMU["Reference emulator"]
  BIN --> ROM["RTL / FPGA / ASIC ROM"]
  ROM --> CPU["Fetch → Execute → Writeback"]
  CPU --> BUS["Valid-ready arbiter and fabric"]
  BUS --> MEM["ROM / SRAM"]
  BUS --> IO["UART / timer / GPIO"]

Loading

Verification and build commands

make test       # Rust, firmware, RTL units, pipeline, SoC, and random differential
make lint       # rustfmt, Clippy, and SystemVerilog lint
make formal     # six Yosys SAT proof jobs
make synth      # portable technology-independent Yosys synthesis
make fpga       # TinyFPGA BX repository-demo bitstream and timing report
make fpga PROGRAM=verification/programs/gpio_soc.s
make asic       # Sky130 full/shuttle mapping plus mapped-netlist UART simulation

Current measured results:

Result	Evidence
Rust tests	26 passing
RTL unit benches	10 passing
Random differential	20 seeds, 2,767 retirements, 194 ordered stores
Formal	6 SAT jobs passing
TinyFPGA BX	6,455 / 7,680 LCs, 4 BRAMs
TinyFPGA BX timing	28.65 MHz estimated fmax at 16 MHz target
Full Sky130 mapping	407,793.6 µm² pre-layout cell area
Shuttle mapping	121,323.9 µm² pre-layout cell area
Sky130 gate simulation	16 UART bytes, HALT, 22,287 cycles

See STATUS.md for exact limitations. Pre-layout ASIC cell area is not a claim of routed die area or fabrication signoff.

Repository map

• rtl/ - core, decode, ALU, CSR, bus, memories, peripherals, and wrappers
• isa/ - opcode registry and Rust encoding definitions
• emulator/ - architectural reference machine and CLI
• assembler/ - assembler and flat-binary builder
• firmware/ - startup and example programs, including demo
• verification/ - unit benches, directed programs, formal harnesses, expected data
• fpga/ - generic/iCE40 synthesis, TinyFPGA BX constraints and build
• asic/ - Sky130 synthesis, SDC, LibreLane config, and Tiny Tapeout metadata
• scripts/ - build and verification scripts
• reports/ - committed measured FPGA and ASIC summaries
• .github/workflows/ - push/PR regression and scheduled hardware jobs

Documentation

• Architecture, ISA, pipeline
• Memory map and bus, peripherals
• Interrupts and exceptions, ABI
• Assembler, binary format, emulator
• Verification, verification summary
• FPGA, synthesis, fabrication
• Release notes

Current limitations

• FPGA placement/routing and timing pass, but no physical board was available for electrical UART/GPIO observation.
• Sky130 synthesis and functional gate simulation pass; placement, routed STA, DRC, LVS, antenna, IR-drop, pad/ESD, and official shuttle tile fit are not signed off.
• Standard-cell memories dominate ASIC area; a fabrication candidate should use qualified SRAM/ROM macros or an external memory interface.
• Formal results are bounded/local safety proofs, not unbounded whole-ISA equivalence.

License

Apache License 2.0. External PDKs and EDA tools retain their own licenses.