sfc: CX4 accuracy improvements

ares/component/processor/hg51b/hg51b.cpp

@@ -20,7 +20,7 @@ auto HG51B::halt() -> void {
 auto HG51B::wait(n24 address) -> u32 {
   if(isROM(address)) return 1 + io.wait.rom;
   if(isRAM(address)) return 1 + io.wait.ram;
-  return 1;
+  return 0;
 }
 
 auto HG51B::main() -> void {
@@ -73,20 +73,24 @@ auto HG51B::suspend() -> void {
 auto HG51B::cache() -> bool {
   n24 address = io.cache.base + r.pb * 512;
 
-  //try to use the current page ...
-  if(io.cache.address[io.cache.page] == address) return io.cache.enable = 0, true;
-  //if it's not valid, try to use the other page ...
-  io.cache.page ^= 1;
-  if(io.cache.address[io.cache.page] == address) return io.cache.enable = 0, true;
-  //if it's not valid, try to load into the other page ...
-  if(io.cache.lock[io.cache.page]) io.cache.page ^= 1;
-  //if it's locked, try to load into the first page ...
-  if(io.cache.lock[io.cache.page]) return io.cache.enable = 0, false;
+  if(io.cache.preload == 0) {
+    //try to use the current page ...
+    if(io.cache.address[io.cache.page] == address) return io.cache.enable = 0, true;
+    //if it's not valid, try to use the other page ...
+    io.cache.page ^= 1;
+    if(io.cache.address[io.cache.page] == address) return io.cache.enable = 0, true;
+    //if it's not valid, try to load into the other page ...
+    if(io.cache.lock[io.cache.page]) io.cache.page ^= 1;
+    //if it's locked, try to load into the first page ...
+    if(io.cache.lock[io.cache.page]) return io.cache.enable = 0, false;
+  }
+  io.cache.preload = 0;
 
   io.cache.address[io.cache.page] = address;
   for(u32 offset : range(256)) {
     step(wait(address));
     programRAM[io.cache.page][offset].byte(0) = read(address++);
+    step(wait(address));
     programRAM[io.cache.page][offset].byte(1) = read(address++);
   }
   return io.cache.enable = 0, true;

ares/component/processor/hg51b/hg51b.hpp

@@ -156,6 +156,7 @@ struct HG51B {
     struct Cache {
       n1  enable;
       n1  page;
+      n1  preload;
       n1  lock[2];
       n24 address[2];  //cache address is in bytes; so 24-bit
       n24 base;        //base address is also in bytes

ares/component/processor/hg51b/registers.cpp

@@ -12,13 +12,13 @@ auto HG51B::readRegister(n7 address) -> n24 {
   case 0x2e:
     io.bus.enable  = 1;
     io.bus.reading = 1;
-    io.bus.pending = 1 + io.wait.rom;
+    io.bus.pending = io.wait.rom;
     io.bus.address = r.mar;
     return 0x000000;
   case 0x2f:
     io.bus.enable  = 1;
     io.bus.reading = 1;
-    io.bus.pending = 1 + io.wait.ram;
+    io.bus.pending = io.wait.ram;
     io.bus.address = r.mar;
     return 0x000000;
 
@@ -76,13 +76,13 @@ auto HG51B::writeRegister(n7 address, n24 data) -> void {
   case 0x2e:
     io.bus.enable  = 1;
     io.bus.writing = 1;
-    io.bus.pending = 1 + io.wait.rom;
+    io.bus.pending = io.wait.rom;
     io.bus.address = r.mar;
     return;
   case 0x2f:
     io.bus.enable  = 1;
     io.bus.writing = 1;
-    io.bus.pending = 1 + io.wait.ram;
+    io.bus.pending = io.wait.ram;
     io.bus.address = r.mar;
     return;
 

ares/sfc/coprocessor/hitachidsp/memory.cpp

@@ -200,7 +200,11 @@ auto HitachiDSP::writeIO(n24 address, n8 data) -> void {
 
   case 0x7f48:
     io.cache.page = data.bit(0);
-    if(io.halt) io.cache.enable = 1;
+    if(io.halt) {
+      r.pb = io.cache.pb;
+      io.cache.preload = 1;
+      io.cache.enable = 1;
+    }
     return;
 
   case 0x7f49: io.cache.base.byte(0) = data; return;