GitHub - b1shtream/conv_differentiable_logic_gate_networks: Deploying logic gate networks on FPGAs for faster Edge AI Inference[Implementation of Differentiable Logic Gate Networks (NeurIPS 2024)] · GitHub

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conv_differentiable_logic_gate_networks

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Deploying logic gate networks on FPGAs for faster Edge AI Inference[Implementation of Differentiable Logic Gate Networks (NeurIPS 2024)]

arxiv.org/abs/2411.04732

fpga logic-gate-network low-bit-quantization neural-network-architectures neural-networks-on-fpga

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Name		Name	Last commit message	Last commit date
data-mnist/MNIST/raw		data-mnist/MNIST/raw
mnist_l		mnist_l
mnist_s		mnist_s
README.md		README.md
difffork.peri.xml		difffork.peri.xml
difffork.xml		difffork.xml
input.vcd		input.vcd
input_mnist20x20.py		input_mnist20x20.py
input_mnist28x28.py		input_mnist28x28.py
lgn.v		lgn.v
lgn_cons.sdc		lgn_cons.sdc
logicGateNet.v		logicGateNet.v
mnist_dataset.py		mnist_dataset.py
output.vcd		output.vcd
requirements.txt		requirements.txt
uart_rx.v		uart_rx.v
uart_tx.v		uart_tx.v

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Implementation based on the paper Convolutional Differentiable Logic Gate Networks

Setup

Python Version: 3.9.21

FPGA: Efinix Trion 120

UART RX: GPIOT_RXN28

UART TX: GPIOT_RXP28

Clock: GPIOR_188 (PLL_BR2)

Clock frequency: 5MHz

Constraint: 200ns

More details on

Experiments details: https://github.com/b1shtream/difflogic_fork/blob/main/experiments.md

Blog: https://riyabisht.com/blog/a_short_primer_on_hardcoded_inference_on_fpgas/

Slides: https://docs.google.com/presentation/d/146nOXXAlzo0-uFZdrOXM_8YubzIWtEXlrnBbdgDeBLg/edit

Training Demo: https://vimeo.com/1095090852

Training framework: https://github.com/b1shtream/difflogic_fork

Mail me if you want to view full bachelors thesis on this project.

About

Deploying logic gate networks on FPGAs for faster Edge AI Inference[Implementation of Differentiable Logic Gate Networks (NeurIPS 2024)]

arxiv.org/abs/2411.04732

fpga logic-gate-network low-bit-quantization neural-network-architectures neural-networks-on-fpga

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