CX4: DMA timing fix

[AkiteruSDA]

DMA to internal RAM was taking 2+WS cycles per byte instead of 1+WS as described in ikari's RE notes. I fixed this by removing the extra cycle that was being added on internal RAM access. This primarily fixes excessive slowdown during the Morph Moth fight: https://www.youtube.com/watch?v=b8YtjKAxtGU

All tests in cx4test pass (see here for a fixed cx4test ROM and details.)

[Max833]

That's great! Thank you! ^_^ Is there a way that you make a fix for ares as well? :D https://github.com/ares-emulator/ares

[Screwtapello]

Just to verify I'm understanding things correctly, when you say "as described in ikari's RE notes", you specifically mean the sentence:

DMA from/to internal RAM only takes WS1 or WS2 extra waitstates depending on the referenced mapping area.

The Cx4's DMA has four ends (cartridge ROM, cartridge save RAM, the Cx4 internal instruction cache, and the Cx4 control registers). DMA from cart ROM to the instruction cache incurs 1-8 waitstates for talking to ROM (configurable as "WS1"), but no waitstates for talking to the internal RAM. DMA from the instruction cache to save RAM incurs 1-8 waitstates for talking to RAM (configurable as "WS2") but no waitstates for talking to the internal RAM.

Have I understood all that correctly?

[AkiteruSDA]

Yeah, that's right. Technically the program cache isn't addressable via normal DMA, only by cache preloads and cache misses at runtime, but the timings are the same. 1+WS1 from ROM to internal RAM (or program cache), 1+WS2 from internal RAM to SRAM, 1+WS1+1+WS2 from ROM to SRAM.

[Screwtapello]

Thanks!