Vitis Unified Backend - #1376

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Tanawin1701d wants to merge 111 commits into

fastmachinelearning:mainfrom

Tanawin1701d:VitisUnifiedClean

Commits on Aug 14, 2025

add vitisUnified backend and its writer
Tanawin1701d
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3922260
add vitis unified template
Tanawin1701d
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6ac2b71

Commits on Aug 15, 2025

add dma wrapper access
Tanawin1701d
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cfc92d5
extract writer class + add gmem wrapper
Tanawin1701d
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f570c3f
extract writer class + add gmem wrapper
Tanawin1701d
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1169bf4
fix store value override
Tanawin1701d
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a772aeb
draft write_hls initialization
Tanawin1701d
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235bc2d
fix import bug at VitisUnifiedwriter
Tanawin1701d
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2c5a6e8
add project generation and .h file generation
Tanawin1701d
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fd4f3d6

Commits on Aug 16, 2025

Commits on Aug 17, 2025

update build function for vitis unified
Tanawin1701d
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3f6d224
add bridge simulation
Tanawin1701d
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19e0af9
add bridge script and move a bit bridge generator
Tanawin1701d
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32d079b
change build script permission and refactoring cosim writing
Tanawin1701d
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9237af5
add cosim testbench + fix namming in gmem
Tanawin1701d
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bd6a384
fix wrapper mismatch io bug and testing the bridge simulation
Tanawin1701d
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c1b95c9

Commits on Aug 18, 2025

add .bit file for full flow
Tanawin1701d
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6e37f3c
add python generator for the system
Tanawin1701d
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f64b50d

Commits on Aug 20, 2025

divert tot use mg and add mgs group generator
Tanawin1701d
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548a8f0
add sub-writer override for vitis unified/unified partial
Tanawin1701d
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abf830f
register backend and writer
Tanawin1701d
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485c1c8
fix minor missing syntax
Tanawin1701d
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d78a50d
fix wrap_gen syntax bug + add include ap_axi_sdata.h for wrapgen + add automatic magic streamer composer
Tanawin1701d
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d23e591
add magic streamer generator and auto invoker
Tanawin1701d
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6cce4ea

Commits on Aug 21, 2025

add icap wraper and magic seq
Tanawin1701d
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7d99de6

Commits on Aug 22, 2025

add project builder tcl file copy
Tanawin1701d
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c1e2419

Commits on Aug 23, 2025

integrating the zcu102 synthesis code
Tanawin1701d
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ccd3d2a
add connection between block
Tanawin1701d
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b982b21

Commits on Aug 24, 2025

drafting the automatically magic streamer linker
Tanawin1701d
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0b3debc

Commits on Aug 25, 2025

add new refactor magic streamer controller
Tanawin1701d
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d4220c4
add start converter for class MgsModel
Tanawin1701d
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e81078a
fix mgs model syntax bug
Tanawin1701d
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05cc849
fix syntax generation for vitisUnified partialbackend
Tanawin1701d
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fe9fe8b
send magic streamer manager to writer
Tanawin1701d
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7b1b12b
specify io signal meta-data to tcl file for each configuration
Tanawin1701d
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b2f2238
add build for stitcher
Tanawin1701d
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654724a
update vivado project stitcher script
Tanawin1701d
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95148d8

Commits on Aug 26, 2025

delete vitis Unified partial after merge the co-reactor
Tanawin1701d
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3de0444
delete vitis Unified partial template
Tanawin1701d
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3e1314c
fix bridge gen top function name change
Tanawin1701d
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e367146
clean vitis config: test using bridge test and it pass
Tanawin1701d
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ac04d40
add to check accept only io stream
Tanawin1701d
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dfbbc3d
add bridge gen to support both float and double input
Tanawin1701d
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04d0e6d
fix size getting bug in cosim
Tanawin1701d
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b77e22f
fix config to gen two kernel hardware cfg for csim and csim
Tanawin1701d
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e14f2c6

Commits on Aug 27, 2025

Commits on Aug 28, 2025

push fifo
Tanawin1701d
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0525079
upgrade new wrapper
Tanawin1701d
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671c1ae
upgrade the parameter of cosim and bridge sim
Tanawin1701d
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f5189b9
fix missing wrap problem
Tanawin1701d
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2d83c57

Commits on Aug 29, 2025

fix missing wrap problem
Tanawin1701d
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fbf1dee
update the driver and testing
Tanawin1701d
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1ece84e
push ready to test code and its example driver
Tanawin1701d
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143ae14
delete polute file and unconment the compile
Tanawin1701d
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7097f63
remove debug print on multigraph
Tanawin1701d
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48e49d4
change xpfm default Path
Tanawin1701d
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d588181
revert the multigraph modification because it is not relate to this branch at all
Tanawin1701d
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b2ee0e3
get the code out that not related to vitisUnified backend
Tanawin1701d
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b17d2b2

Commits on Sep 2, 2025

update code to precommit style
Tanawin1701d
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3f6a37e
fix vitisConfig missign (after refactor) add comment
Tanawin1701d
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48d7500
fix ciricular import again
Tanawin1701d
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0feaf32

Commits on Feb 10, 2026

add bridge sim for axi stream
Tanawin1701d
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c2e5209

Commits on Feb 12, 2026

fix support fifo-op, driver_gen, auto_link for axi stream
Tanawin1701d
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3970b21

Commits on Feb 13, 2026

update driver template for both axis and axim
Tanawin1701d
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ac34e21
refactor the generated file naming
Tanawin1701d
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a62044f
pass test both axi_stream and axi_master/ add dedicated example ipynb
Tanawin1701d
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611b8d8

Commits on Feb 14, 2026

clean code/ cut out unused argument/ use pytest
Tanawin1701d
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e22ac46

Commits on Feb 17, 2026

Commits on Feb 19, 2026

Commits on Feb 21, 2026

Merge pull request #1 from nghielme/vitis-unified-pr
Tanawin1701d
authored
e540553

Commits on Feb 23, 2026

Merge branch 'main' into VitisUnifiedClean
nghielme
authored
28dc178

Commits on Feb 25, 2026

Commits on Feb 26, 2026

restructure the template repository
Tanawin1701d
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86e7211
restructure a supported_boards.json
Tanawin1701d
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d69d15e
fix return execution's profile
Tanawin1701d
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4dbc6b3

Commits on Feb 27, 2026

Commits on Feb 28, 2026

update tlast stream and stream driver
Tanawin1701d
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bd5951a
fix axi stream driver performance bug
Tanawin1701d
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36b4947

Commits on Mar 1, 2026

unified the IP driver and NN driver wrapper
Tanawin1701d
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a45f5e4

Commits on Mar 5, 2026

fix vitis unified compute bug and add performance tracker to the system
Tanawin1701d
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0a8c6d3
delete tlast stream parameter
Tanawin1701d
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ad7c66f

Commits on Mar 10, 2026

Merge branch 'main' into VitisUnifiedClean
nghielme
authored
f1f1c76

Commits on Mar 20, 2026

Added updated script for creating board design for KV260 with Vivado 2025.2.
lolbraa
committed
9e86b42

Commits on Apr 24, 2026

Passing -force when creating Vivado project to overwrite existing project
lolbraa
committed
4bf6624

Commits on May 7, 2026

Fixed part for board kv260, extracted from Vivado part list. Tested with both Vivado 2023.2 and 2025.2.
lolbraa
committed
79dc505

Commits on Aug 13, 2026

Merge pull request #2 from lolbraa/VitisUnifiedClean
Tanawin1701d
authored
a26b52d
[pre-commit.ci] auto fixes from pre-commit hooks
pre-commit-ci[bot]
committed
017744e
Merge branch 'main' into VitisUnifiedClean
JanFSchulte
authored
a3049a9