MAC Unit RTL → GDSII

Complete ASIC Implementation using Verilog HDL, OpenLane & Sky130 PDK

---

Overview

A Multiply–Accumulate (MAC) unit is a digital hardware block widely used in Digital Signal Processing (DSP) and computer architectures.

This repository demonstrates the complete RTL → GDSII ASIC implementation flow of a custom 4-bit MAC Unit using Ubuntu, OpenLane, and the Sky130 Process Design Kit (PDK).

The overall ASIC implementation flow remains the same across platforms (Ubuntu, Azure VM, etc.); only the installation and terminal commands vary slightly.

---

MAC Unit Architecture

Figure 1. MAC Unit Block Diagram

---

Project Setup

Navigate to the OpenLane directory and follow the steps below.

Step	Description
Step 1	Create a new project directory. mkdir MAC_unit
Step 2	Move into the project directory. cd MAC_unit
Step 3	Create the src directory. mkdir src
Step 4	Move into the source directory and create the CLA module. cd src gedit cla.v Paste the CLA Verilog code, save the file, and close the editor.
Step 5	Repeat the same process for: multiplier.v acc.v mac.v mac_tb.v After creating each file, verify using ls
Step 6	Return to the project directory. cd ..
Step 7	Create the OpenLane configuration file. gedit config.json Paste the configuration code and save it.

Figure 2. Terminal View

---

RTL Simulation

Move into the src directory and compile the design.

iverilog -o mac_sim acc.v cla.v multiplier.v mac.v mac_tb.v

Run the simulation.

vvp mac_sim

After successful execution, the terminal should display the simulation output.

Figure 3. RTL Simulation Output

---

GTKWave Verification

Open the waveform.

gtkwave dump.vcd

Inside GTKWave:

• Select tb_mac_unit
• Add the required signals
• Adjust the zoom level to inspect the waveform

Figure 4. GTKWave Verification

---

RTL → GDSII Flow

Return to the OpenLane directory.

cd ~/OpenLane

Launch the Docker container.

make mount

Run the complete OpenLane flow.

./flow.tcl -design MAC_unit

OpenLane will automatically perform:

• RTL Elaboration
• Logic Synthesis
• Floorplanning
• Placement
• Clock Tree Synthesis
• Routing
• DRC
• LVS
• GDSII Generation

Ignore minor warnings if present. The important message is:

SUCCESS : Flow Complete

---

KLayout Visualization

Locate the generated GDSII file.

find . -name "*.gds"

Open the generated layout.

klayout <path_to_gds_file>

Figure 5. Generated GDSII File

Figure 6. KLayout View

---

3D GDS Visualization

Copy the generated .gds file and upload it to

Tiny Tapeout GDS Viewer

https://gds-viewer.tinytapeout.com/

Figure 7. 3D Visualization of the Final GDSII Layout

---

Source Files

The project consists of the following Verilog modules.

File	Description
multiplier.v	Sequential Shift-and-Add Multiplier
cla.v	17-bit Carry Lookahead Adder
acc.v	17-bit Accumulator
mac.v	Top-level MAC Module
mac_tb.v	Functional Testbench
config.json	OpenLane Configuration

---

Conclusion

The complete RTL → GDSII implementation of the MAC Unit has been successfully demonstrated.

This design can be further extended into:

• Multi-MAC Arrays
• Pipelined Architectures
• Systolic Arrays
• Matrix Multiplication Engines
• CNN / AI Accelerators
• FPGA Implementations

---